Semiconductor Engineering

Can We Efficiently Automate 2.5/3D IC ESD Protection Verification?

Protection against ESD events (commonly referred to as ESD robustness) is an extremely important aspect of integrated circuit (IC) design and verification, including 2.5/3D designs. ESD events cause ...
Design-Reuse

Specialty Analog ESD IO IP, BOAC (Bonding Over Active Circuit), UMC 0.13um LL/FSG process

UMC 0.13um LL/FSG Logic process 3.3V AnalogESD IO with POC (Pad On Circuit).
Semiconductor Engineering

2.5/3D IC Reliability Verification Has Come A Long Way

2.5D/3D integrated circuits (ICs) have evolved into an innovative solution for many IC design and integration challenges. As shown in figure 1, 2.5D ICs have multiple dies placed side-by-side on a ...
EDN

Automate ESD protection verification for complex ICs

Designing an integrated circuit (IC) for communication, computing, gaming, and other emerging applications is a multi-million dollar project, requiring rigorous design methodology and substantial ...
Design-Reuse

Krivi announces availability of 28nm UMC IO Pad library platform

BANGALORE, India --, July 8, 2015 —Krivi Semiconductor has announced availability of its Alcor IO pad library platform for UMC’s 28nm technology. This IO platform supports a wide variety of interface ...